3PAR V-Class: The Best Just Got Better

By | September 16, 2011

Disclaimer: I’m a self confessed fan of the 3PAR architecture.  I think its best and cleanest design of all of the enterprise class storage arrays on the market.  But I admit that architecture isn’t everything, service, support, cost etc all play a part in the wider solution.

Anyway, now that that is out of the way….  It’s old news that HP recently announced a major refresh of it’s 3PAR line, the P10000 or 3PAR V-Class.  I despise HP’s naming conventions so I will call it V-Class.

One potentially interesting thing to note from the product branding P10000 (that’s ten thousand) is that HP have given the 3PAR a higher number than the rebadged Hitachi VSP, the HP P9500.  Generally speaking with HP storage products, the higher the number the bigger and more enterprise the array (that’s my interpretation anyway) –

P2000 = MSA.  Aimed at small businesses

P4000 = LeftHand iSCSI array.  Aimed at SMB

P6000 = EVA.  Aimed at SMB

P9500 = OEM’d Hitachi VSP.  Aimed squarely at high end enterprises

So one would naturally assume that something with a higher number than the P9500 to be… well….. more “enterprise”.

Anyway lets get to the good stuff……

The Good Stuff

For me, the major improvements that came with the V-Class are the following –

  • Moving from PCI-X to PCIe
  • 4th generation ASIC
  • Peer Motion

Aside from the innovations listed above, the V-Class just feels more enterprise, more high performance.  Things like 2 x 4th gen ASIC per controller node, compared to the previous generation T-Class only having 1 x 3rd gen ASIC per controller.  Similarly there is 2 x quad core CPU’s per controller node versus 2 x dual core in previous generations.  Then there’s more than doubling the available control and data cache per node as well as the inclusion of T10 DIF support.  All in all, it feels like it now has the muscle to stand it’s ground against VMAX and VSP.

The Stuff Thats Missing

Of course it’s not perfect.  On the Negative side the following are disappointments –

  • No 2.5-inch drive form factor. Only option remain 3.5-inch. This is behind the curve and a disappointment.
  • No SAS backend.  The backend remains switched FC-AL and while I appreciate that this allows large distances between the controllers and disk cabinets I’m unsure how enterprise this is.  Don’t get me wrong, I like the idea, but I’m not sure I’d want to bet my entire array on a single FC cable routed under the floor and across to the other side of the data centre hall!?  Also, the switch to SAS as the backend of choice is well under way.
  • No de-duplication or compression. Not that anybody else does this either, but with the knowing that the 4th gen ASIC was on its way I wondered whether we might have seen these features. If HP/3PAR had come to market with this then that would have seen them widely recognised as a leader again.

PCIe

I won’t spend long on this.  I think it speaks for itself.

While I’ve been a long time fan of the 3PAR architecture, I’ve always been a little embarrassed of the PCI-X architecture.  It’s old technology and has no place in a modern and innovative high performance storage array.  Anyway, its gone, so let’s never speak of it again.

4th Gen ASIC

Why do I care about ASICs, FPGAs and things like that?

While I agree that I shouldn’t really care as long it performs well and stays on its feet, knowing what is under the hood and how something is put together helps you in all kinds of ways.

              For me, custom silicon (ASIC) has its place in high end of storage arrays for at least another 5 years.  Offloading certain functions to ASICs is more efficient and allows for higher performance.  Not too dissimilar to the approach VMware has taken of late where it offloads functions through VAAI to the storage array.  The concept is simple, offload specialised tasks to the expert – VMware offloads storage tasks to the storage array, similarly within a 3PAR array, InForm offloads certain storage related tasks to the specialised silicon (ASIC).

              Hitachi agree with this approach and the VSP (P9500 in HP parlance) has taken a very similar approach.

              For deep technical discussion on the use of custom ASICs in storage arrays listen to the recent “Odds and SODs” episode of the Infosmack Deep Dive podcast that I host.

              Peer Motion: More Than a Get Out of Jail Card

              At a high level, Peer Motion promises to simplify migrating data between arrays, and potentially federate those arrays into teams of loosely coupled arrays. 

              The hope from customers will be that Peer Motion will allow them to dynamically and non-disruptively move workloads between arrays – similar to the way that auto-tiering products dynamically move extents between different tiers of storage…. 

              One immediate use case may be as a get out of jail card that allows for more aggressive overprovisioning.  The worry about overprovisioning has always been “what do I do when I can no longer add capacity to my overprovisioned array?”.  I for one would feel a lot more comfortable aggressively overprovisioning if I knew I had a technology their that could migrate apps to another array and thus free us space on the old array…..

              Another no-brainer use case will be tech refresh.  Many large organisations struggle hugely with tech refresh. They buy technology and cant get off it.  And this isn’t always vendors trying to lock them in. Many times organisations can’t even seamlessly move to the next gen architectures from the same vendor!

              If HP/3PAR manage to nail this in true 3PAR style (simple and efficient) then I will be extremely impressed and HP can expect many happy customers.

              At day 1 it looks like Peer Motion will allow non-disruptive migrations between any 3PAR systems.  Roadmapped, no doubt, will be heterogeneous Peer Motion.

              Summing It Up

              If 3PAR didn’t have a truly enterprise class high performance model before, they do now!

              If VMAX and VSP didn’t see 3PAR as competition at the high end before, they will now!

              If you wouldn’t consider 3PAR in the past, may be you should now.

              All in all this is a good move forward.  While like the move to PCIe and the 4th Gen ASIC, the real killer feature is Peer Motion.  If HP/3PAR nail this they are on to a winner.

              However, most of the work that went in to this refresh will have been well under way when HP bought 3PAR.  So this should be seen as a true 3PAR array with probably very little HP influence (good or bad). 

              Now the onus is on HP to invest and give 3PAR the space to continue to innovate.  On the other hand, the worry is that HP may starve and strangle 3PAR.

              Comments welcome, and don’t forget to tune in to the Deep Dive podcast I do over at infosmackpodcasts.com.  We try and generate high quality technical discussion on a broad range or enterprise tech topics.

              Nigel

              18 thoughts on “3PAR V-Class: The Best Just Got Better

              1. Nigel Poulton Post author

                Barry,

                Good to hear from you and thanks for getting involved.

                Let me qualify my statement on ASICs having a place in high end storage for another 5 years.  I am not suggesting that the next 3PAR array, V-Class mk 2 if you will, will have a Gen 5 ASIC.  Possibly not. 

                What I AM saying is that I believe the benefits of ASICs will be seen in high end storage arrays for the next 5 years.  VSP and 3PAR V-Class will still be around then and are currently best in class in my opinion.

                I also believe that I'm right in saying that VMAX (you mention that EMC went commodity with VMAX) still has custom EMC silicon inside.  RapidIO functions are offloaded to a custom EMC designed ASIC and then there is the data encryption at rest stuff that is done in an ASIC (in the tachyon processor although is not EMC designed silicon).  So things are not as clean cut as you may be suggesting.

                Its an interesting discussion and one we may have to get you on the podcast to discuss.

                Nigel

              2. Barry Whyte

                Be happy to join the podcast and discuss, while we too use the same PMC FC chip- you maybe interested to know that PMC have decided not to develop a 16Gbit version… something about not being profitable,… if the podcast recordings aren;t at 12am – i'd be happy to defend my corner 🙂

              3. TimC

                Ya, x86 CPU's are the only way to go.  Just look at the only "enterprise" array IBM sells, the DS8800.  It has no custom ASIC's and uses x86 CPU's… er…

                Nigel: he's talking out of the side of his mouth.  Claiming ASIC's are already obsolete when they use them in their own storage line-up.  I'd just ignore him since he apparently can't even keep track of his own product line.

              4. Barry Whyte

                Tim, i think you'll find I mentioned both x86 and Power in my post…

                The only ASIC in the DS8K is the PCIe chip used in the HA and DA cards which gives the protocol and Z interfaces – as nobody in the OEM market prduces an HBA with Z function.
                I'm quite aware of our product line thank you, and what I'm talking about here is custom asic design for offload functions, i.e. zero detect, etc – there is no need for that these days, nor things like RAID XOR, when the power in a base cores and inbuilt 64bit memory extensions etc

              5. Burak

                Nigel,
                I think HP will favor 3PAR over VSP 9500 simply because they own them therefore assigning them a higher number 10000. More profit, more control. It is a bit like Dell throwing dirt on EMC because they acquired Compellent. Can you expand a little more on the 'peer motion'? I thought the virtual structure of VMAX and VSP allowed you to bring in 3rd party storage devices so called scale-out.
                I guess if 3PAR stuff is better than VSP's why should they keep the 9500 line. It will be interesting to see.

              6. Nigel Poulton Post author

                Burak,

                There are cases where a P9500 would be required over a 3PAR. Mainframe attach is one of them, but that is very niche in my opinion as I dont imaging many Mainframe shops buy storage from HP.

                There are other cases but the overlap between P9500 and 3PAR v-Class is now huge and will only confuse customers and sales forces alike.

                Just my penny worth.

                BTW I will expand on Peer Motion a little later, time for dinner!

              7. Nigel Poulton Post author

                Barry,

                Curious, when you say that writing 100 lines of Intel assembler is more code efficient and more MIPS efficient than creating an ASIC, does this also translate in to customer benefits, or is this all just to make the vendors development cycle shorter, cheaper and easier?

                Back to the custom discussion….. You could say that a 3PAR and VSP/P9500 systems are entirely custom built for storage, not just the ASICs. And I would personally add that as such, both are better at storage than something like a DS8 (I know you are not a DS8 person but we’re talking scalable enterprise arrays here…). Its not just the ASIC, its the entire design of the arrays. These arrays are conceived and built with storage in mind. The DS8, well, looks like a couple of AIX machines cobbled together with a few disk shelves. And I personally think it shows. VSP and 3PAR are much slicker all way from chunklets on the physical disks (3PAR) through the TP extents all the way to performance seen by hosts. I can only imagine IBM DS8 winning against VSP and 3PAR in Mainframe shops or shops that are wall to wall IBM.

                SVC and V700 are different animals altogether and have a lot more going for them than DS8. But they serve different markets and needs than 3PAR V-Class and VSP. Horses for courses?

                I still stand by my point that custom silicon has its place in high end storage for a few years yet. I know DS8 has no IBM custom silicon in it, but then I dont think DS8 belongs in the same league as 3PAR and VSP.

                Great discussion by the way.

                Nigel

              8. Nigel Poulton Post author

                TimC,

                Thanks for your input.

                Mind you, I can’t imagine Barry ever being out of touch with the IBM storage product line… 

                I should point out that I know Barry and respect him a lot.  However, that doesn’t stop him being wrong in this particular discussion.  Not a big issue though, after all he works in midrange storage 😛

              9. Barry Whyte

                Nigel, 

                Indeed, good discussion, and you make some valid points, (mutual respect and all that), I guess we will see custom ASICs for a while longer, however the main point I was making is that it isn't necessary any more, the main historical reason has been performance, where custom hardware was always faster than using commodity parts and writing code to run on them. This I'd say is no longer the case, and as such more vendors will "see the light" and switch to using commodity parts, not only because its cheaper from a dev point of view,  but also because it benefits our customers – quicker to dev and test, therefore more value can be added elsewhere in delivering more advanced software functions.
                Guess time will tell 🙂

              10. Nigel Poulton Post author

                Barry I hear what you’re saying about quicker dev test and more value being added in advanced functions. However, I have to admit that I absolutely do not see it in the real world.

                I’d love some examples.

                The way I see it, at the high end, the 3PAR and the VSP have the custom silicon as well as the advanced features and many of them before the competition…..

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              15. David Warburton

                 

                Great article, thank you!
                I'm pretty new to 3Par but getting in to it more now that we'll be deploying them for internal use as well as for a multi-tenant cloud environment. 
                I was also disappointed at the lack of de-dupe! They bang on about Thin-everything, but no sign of de-dupe. Coming from a Netapp background I have seen really good savings and performance on de-duped volumes.
                Is this something on the roadmap to be added to existing models?
                Keep up the good work, here and on the podcasts! 🙂

              16. Brian Rawlings

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                Nigel's point about ASIC-driven arrays is supported by the facts – to wit, the SPC-1 benchmark and the new HP/3Par V800 (AKA the P10000, sorry Nigel).  I submit the following to back up my statements:

                IBM SVC 4-node SPC-1 benchmark is 315,000 IOPS.  The IBM SVC 6-node SPC-1 is 380,489 IOPS.  Both are based on pretty recent, pretty fast commodity INTEL quad-core 5500 processors, 8 total in the 4-node cluster and 12 total in the 6-node cluster.  Both are fronting a pair of DS8700s with a total 15K RPM drive count of 2048.
                I notice two things when I compare this with the 450,000 IOPS produced by the ASIC-driven 3Par V800 8-node system with its 1920 15K RPM spindles.  The first is fairly obvious – with all the heavy lifting done by the Gen-4 ASICs, the 3Par unit pretty much stomps the heck out of the no-ASIC SVC and its mostly ASIC-free DS8700s.  I'm not sure how many POWER processors there are in the pair of DS8700s, but add the power of those to the 32 or 48 cores of INTEL power, and 3Par still whups 'em good, with power to spare.  So, yes, the special purpose ASIC still has its place in the grand scheme, and will very likely continue to, for at least the 5 years that Nigel proposes.
                The second thing is a bit more subtle, but even more telling in favor of custom silicon, or so it seems to me.  The 4-node SVC pumps out 315K IOPS, and the 6-node SVC cluster pumps out 380.5K IOPS.  For the addition of 50% more nodes, we get about 20% more IOPS.  This may well be why IBM has not posted an 8-way SPC-1 benchmark – with all the intra-node traffic, keeping memory maps in sync, cache mirrored, etc, there appears to be a tremendous drop-off in additional performance as you add nodes, at least in a commodity processor and interlink world.
                Since the Gen-4 ASIC also handles all of these intra-node tasks for 3Par, however, there is very near to linear scaling as you add nodes in a 3Par V800.  This is where the power of the ASIC can really be seen, and it is how the V800 posts 450,000 IOPS with FEWER SPINDLES, via the near-wire-speed functionality of the ASIC that lets all system resources – all the IOPS from all the drives, the cache and RAM, and all 8 nodes – come to bear on driving I/O throughput.

                The proof is in the pudding – Nigel's right, the ASIC-based array whips up on the non-ASIC-based pretender to the throne, the numbers are there for all to see.
                [Disclaimer – I don't work for HP or 3Par, but I primarily support the HP line where I DO work… my employer distributes all the top-tier storage and technology products.  The opinions expressed are my own and not necessarily those of anyone else, yada yada yada]

              17. Brian Rawlings

                @David W – I'd be very interested to hear of any positive experiences you may have personally had with Netapp and de-dupe, specifically about performance.  I have a lot of second hand info from various friends and colleagues in various operational and admin roles who have told me that if they needed performance out of the array, they had to basically turn off the de-dupe feature, but for large near-line/SATA arrays where performance was not the top goal, they found that de-dupe returned a useful amount of storage back to the free pool.  Having no Netapps of my own to administer or test, I'm interested in your observation that you've seen "good savings and performance from de-duped volumes".  Can you expand on that at all?  How full were the arrays, what did you notice about impact to performance, etc?
                 
                I do expect that if/when in-place compression, de-dupe, or encryption is added to 3Par's line-up, it will again be the ASIC that will make these features happen at near-wire-speed, and that without an ASIC, you're basically stealing LOTS of cycles from already busy CPUs in the controllers.  We already see this with many non-ASIC-based controllers when you turn on snapshots and thin provisioning and then you add replication to the mix, or find other ways to overtax the CPU/compute side.
                 
                @Nigel – sorry my post is so screwed up, but I had a heck of a time getting past the "captcha" code, and I ended up dropping the text temporarily into a word doc.  Oops.  I can't find a way to clean it up myself, but if you can take a minute to get rid of all the word doc crap it added at the beginnings, maybe I won't sound like a flaming idiot…  or like so much of one.  Thanks all!

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