I caught up with Howard Marks last week when he was in town in London. We went out for a quick bite to eat one night and talked shop for two or three hours. I know my place when in the company of a grey beard like Howard, so for the most part I kept quiet and listened. However at one point I vented my frustration that 3PAR arrays still don’t support flash as a cache – despite being based on a modern innovative architecture supposedly better suited to todays demands and requirements than something like, let’s say an apparently donkey architecture like EMC VNX.
But hang on a minute. EMC VNX has supported flash as cache for ages now. I cant be bothered to look it up, but I reckon VNX has supported flash as a cache (in the form of FAST Cache) for at least 2 years, probably more.
Seriously, I thought the uber-modern architecture of 3PAR was supposed to make adding innovative technologies easier. Could it actually be that the architecture of the box is hindering the adoption of important technologies like flash as a cache! I mean seriously, how long does it take to catch-up to a 20 year old legacy technology like VNX?
Howard suggested that the problem might lie with the 3PAR ASIC.
We know that ASIC design can elongate the innovation cycle when compared to implementing on commodity Intel type architectures, but I honestly never thought that the ASIC might be behind the sloooooow uptake on flash as a cache.
I know that 3PAR support flash as a tier, but I also know that that isn’t always enough. VNX supports flash as a tier and/or as a cache. How can 3PAR be behind?
I have to admit that I’m a fan of the way 3PAR implements thin technologies, and I do believe that implementing thin through the ASIC gives them an edge. But in this case, assuming Howard is correct in assuming that the ASIC is the stumbling block to implementing flash as a cache, it seems the ASIC really is a two-edged sword – the ASIC giveth and the ASIC taketh!
Oh, and since I said Im a fan if how 3PAR implements thin technologies via the ASIC, it is only fair to say that when it comes to flash as a cache implementations, VNX clearly wipes the floor with 3PAR.
QUICK UPDATE: I'm certain that there will be tons of existing, and potential, 3PAR customers with legitimate use cases and requirements for flash as a cache. So surely this will be an engineering priority within HP, and as such would have been implemented by now if it could!?